View ADG774ABCPZ-REEL_5913365.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low voltage, 400 mhz, quad 2:1 mux with 3 ns switching time adg774a rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features bandwidth: >400 mhz low insertion loss and on resistance: 2.2 typical on resistance flatness: 0.3 typical single 3 v/5 v supply operation very low distortion: <0.3% low quiescent supply cu rrent: 1 na typical fast switching times t on = 6 ns t off = 3 ns ttl-/cmos-compatible pb-free packages 16-lead qssop 16-lead 3 mm 3 mm body lfcsp functional block diagram 1 of 2 decoder adg774a en in s1a s1b s2a s2b s3a s3b s4a s4b d1 d2 d3 d4 0 2373-001 figure 1. general description the adg774a is a monolithic cmos device comprising four 2:1 multiplexer/demultiplexers with high impedance outputs. the cmos process provides low power dissipation yet offers high switching speed and low on resistance. the on resistance variation is typically less than 0.5 over the input signal range. the bandwidth of the adg774a is typically 400 mhz and this, coupled with low distortion (typically 0.3%), makes the part suitable for switching of high speed data signals. the on resistance profile is very flat over the full analog input range ensuring excellent linearity and low distortion. cmos construction ensures ultralow power dissipation. the adg774a operates from a single 3.3 v/5 v supply and is ttl logic-compatible. the control logic for each switch is shown in the truth table (see table 5 ). these switches conduct equally well in both directions when on. in the off condition, signal levels up to the supplies are blocked. the adg774a switches exhibit break-before-make switching action. product highlights 1. wide bandwidth data rates of >400 mhz. 2. ultralow power dissipation. 3. low leakage over temperature. 4. break-before-make switching prevents channel shorting when the switches are configured as a multiplexer. 5. crosstalk is typically ?70 db @ 10 mhz. 6. off isolation is typically ?65 db @ 10 mhz. 7. available in compact 3 mm 3 mm lfcsp.
adg774a rev. b | page 2 of 16 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 single supply ................................................................................. 3 absolute maximum ratings............................................................ 5 esd caution...................................................................................5 pin configurations and function descriptions ............................6 typical performance characteristics ..............................................7 test circuits........................................................................................9 terminology .................................................................................... 11 application circuits ....................................................................... 12 outline dimensions ....................................................................... 13 ordering guide .......................................................................... 13 revision history 8/06rev. a to rev. b updated format..................................................................universal added lfcsp model..........................................................universal added lead-free models ..................................................universal changes to table 3.............................................................................5 updated outline dimensions ....................................................... 13 changes to ordering guide .......................................................... 13 4/03rev. 0 to rev. a changes to tpcs 9C11......................................................................5 updated outline dimensions..........................................................8 7/01revision 0: initial version
adg774a rev. b | page 3 of 16 specifications single supply v dd = 5 v 10%, gnd = 0 v, all specifications t min to t max , unless otherwise noted. 1 table 1. b version parameter 25c t min to t max unit test conditions/comments analog switch analog signal range 0 to 2.5 v on resistance, r on 2.2 typ v d = 0 v to 1 v, i s = ?10 ma 3.5 4 max on resistance match between channels, ?r on 0.15 typ v d = 0 v to 1 v, i s = ?10 ma 0.5 max on resistance flatness, r flat(on) 0.3 typ v d = 0 v to 1 v, i s = ?10 ma 0.6 max leakage currents source off leakage, i s (off) 0.001 na typ v d = 3 v/1 v, v s = 1 v/3 v, see figure 17 0.1 0.25 na max drain off leakage, i d (off) 0.001 na typ v d = 3 v/1 v, v s = 1 v/3 v, see figure 17 0.1 0.25 na max channel on leakage, i d , i s (on) 0.001 na typ v d = v s = 3 v/1 v, see figure 18 0.1 0.25 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.001 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 2 t on , t on ( en ) 6 ns typ c l = 35 pf, r l = 50 , v s = 2 v, see figure 22 12 ns max t off , t off ( en ) 3 ns typ c l = 35 pf, r l = 50 , v s = 2 v, see figure 22 6 ns max break-before-make time delay, t d 3 ns typ c l = 35 pf, r l = 50 , v s1 = v s2 = 2 v, see figure 23 1 ns min off isolation ?65 db typ f = 10 mhz, r l = 50 , see figure 20 channel-to-channel crosstalk ?70 db typ f = 10 mhz, r l = 50 , see figure 21 bandwidth ?3 db 400 mhz typ r l = 50 , see figure 19 distortion 0.3 % typ r l = 100 charge injection 6 pc typ c l = 1 nf, see figure 24 , v s = 0 v c s (off) 5 pf typ c d (off) 7.5 pf typ c d , c s (on) 12 pf typ power requirements v dd = 5.5 v digital inputs = 0 v or v dd i dd 1 a max 0.001 a typ 1 temperature range for b ve rsion is ?40c to +85c. 2 guaranteed by design, not subject to production test.
adg774a rev. b | page 4 of 16 v dd = 3 v 10%, gnd = 0 v, all specifications t min to t max , unless otherwise noted. 1 table 2. b version parameter 25c t min to t max unit test conditions/comments analog switch analog signal range 0 to 1.5 v on resistance, r on 4 typ v d = 0 v to 1 v; i s = ?10 ma 6 7 max on resistance match between channels, ? r on 0.15 typ v d = 0 v to 1 v, i s = ?10 ma 0.5 max on resistance flatness, r flat(on) 1.5 typ v d = 0 v to 1 v, i s = ?10 ma 3 max leakage currents source off leakage, i s (off) 0.001 na typ v d = 2 v/1 v, v s = 1 v/2 v, see figure 17 0.1 0.25 na max drain off leakage, i d (off) 0.001 na typ v d = 2 v/1 v, v s = 1 v/2 v, see figure 17 0.1 0.25 na max channel on leakage, i d , i s (on) 0.001 na typ v d = v s = 2 v/1 v, see figure 18 0.1 0.25 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.4 v max input current i inl or i inh 0.001 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 2 t on , t on ( en ) 7 ns typ c l = 35 pf, r l = 50 , v s = 1.5 v, see figure 22 14 ns max t off , t off ( en ) 4 ns typ c l = 35 pf, r l = 50 , v s = 1.5 v, see figure 22 8 ns max break-before-make time delay, t d 3 ns typ c l = 35 pf, r l = 50 , v s1 = v s2 = 1.5 v, see figure 23 1 ns min off isolation ?65 db typ f = 10 mhz, r l = 50 channel-to-channel crosstalk ?70 db typ f = 10 mhz, r l = 50 , see figure 21 bandwidth ?3 db 400 mhz typ r l = 50 , see figure 19 distortion 1.5 % typ r l = 100 charge injection 4 pc typ c l = 1 nf, see figure 24 , v s = 0 v c s (off) 5 pf typ c d (off) 7.5 pf typ c d , c s (on) 12 pf typ power requirements v dd = 3.3 v digital inputs = 0 v or v dd i dd 1 a max 0.001 a typ 1 temperature range for b ve rsion is ?40c to +85c. 2 guaranteed by design, not subject to production test.
adg774a rev. b | page 5 of 16 absolute maximum ratings t a = 25 c, unless otherwise noted. table 3. parameters rating v dd to gnd ?0.3 v to +6 v analog, digital inputs 1 ?0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d 100 ma peak current, s or d 300 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c thermal impedance, ja 16-lead qssop 105.44c/w 2 16-lead lfcsp(3 mm 3 mm) 48.7c/w 2 lead temperature soldering vapor phase (60 sec) 215c infrared (15 sec) 220c reflow soldering (pb-free) peak temperature 260c (+0c/C5c) time at peak temperature 10 sec to 40 sec 1 overvoltages at in, s, or d are clamped by internal diodes. current should be limited to the maximum ratings given. 2 measured with the device soldered on a four-layer board. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution
adg774a rev. b | page 6 of 16 pin configurations and function descriptions in s1a s1b d1 s2a s2b d2 gnd v dd en s4a s4b d4 s3a s3b d3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view (not to scale) adg774a 0 2373-002 02373-028 pin 1 indicator 1 s1b 2 d1 3 s2a 4 s2b 11 s4b 12 s4a 10 d4 9s3a 5 d 2 6 g n d 7 d 3 8 s 3 b 1 5 i n 1 6 s 1 a 1 4 v d d 1 3 e n top view (not to scale) adg774a notes 1. the exposed pad should be tied to gnd. figure 2. qsop pin co nfiguration figure 3. lfcsp pin configuration table 4. pin function descriptions pin no. sop lfcsp neonic function 1 15 in logic control input. 2 16 s1a source terminal 1a. may be an input or output. 3 1 s1b source terminal 1b may be an input or output. 4 2 d1 drain terminal d1. may be an input or output. 5 3 s2a source terminal 2a. may be an input or output. 6 4 s2b source terminal 2b. may be an input or output. 7 5 d2 drain terminal d2. may be an input or output. 8 6 gnd ground (0 v) reference. 9 7 d3 drain terminal d3. may be an input or output. 10 8 s3b source terminal 3b. may be an input or output. 11 9 s3a source terminal 3a. may be an input or output. 12 10 d4 drain terminal d4. may be an input or output. 13 11 s4b source terminal 4b. may be an input or output. 14 12 s4a source terminal 4a. may be an input or output. 15 13 en logic control input. when high, all switches are disabled. 16 14 v dd most positive power supply potential. table 5. truth table en in d1 d2 d3 d4 function 1 x hi-z hi-z hi-z hi-z disable 0 0 s1a s2a s3a s4a in = 0 0 1 s1b s2b s3b s4b in = 1
adg774a rev. b | page 7 of 16 typical performance characteristics 20 0 05 v s /v d (v) r on ( ? ) 16 12 8 4 1234 v dd = 5.0v v dd = 4.5v v dd = 5.5v t a = 25c 02373-003 figure 4. on resistance as a function of drain (v d ) or source (v s ) voltage for v dd = 5 v 10% 20 0 03 . 0 v s /v d (v) r on ( ? ) 16 12 8 4 0.51.01.52.02.5 v dd = 3.0v t a = 25c v dd = 2.7v v dd = 3.3v 02373-004 figure 5. on resistance as a function of drain (v d ) or source (v s ) voltage for v dd = 3 v 10% 20 0 05 v s /v d (v) r on ( ? ) 15 10 5 1234 v dd = 5v +85c ?40c +25c 02373-005 figure 6. on resistance as a function of drain (v d ) or source (v s ) voltage for different temperatures with 5 v single supplies 20 0 03 v s /v d (v) r on ( ? ) . 0 15 10 5 0.51.01.52.02.5 v dd = 3v +85c ?40c +25c 02373-006 figure 7. on resistance as a function of drain (v d ) or source (v s ) voltage for different temperatures with 3 v single supplies 0.025 ?0.025 04 v s /v d (v) current (na) v dd = 5.0v v ss = 0v temp = 25c v d = v dd ? v s 0.020 0.015 0.010 0.005 0 ?0.005 ?0.010 ?0.015 ?0.020 i d (off) i s (off) i s , i d (on) 123 v s 02373-007 . 0 figure 8. leakage current as a function of drain (v d ) or source (v s ) voltage for v dd = 5 v 0.025 ?0.025 03 v s /v d (v) v s current (na) 0.020 0.015 0.010 0.005 0 ?0.005 ?0.010 ?0.015 ?0.020 0.5 1.0 1.5 2.0 2.5 i s (off) v dd = 3.0v v ss = 0v temp = 25c v d = v dd ? v s i d (off) i s , i d (on) 02373-008 figure 9. leakage current as a function of drain (v d ) or source (v s ) voltage for v dd = 3 v
adg774a rev. b | page 8 of 16 temperature (c) current (na) 0.05 ?0.05 58 5 0 ?100 0.01 1000 frequency (mhz) attenuation (db) 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 ?0.04 v dd = 5.0v v ss = 0v temp = 25c v d = 3v/1v v s = 1v/3v ?20 ?40 ?60 ?80 i s , i d (on) i d (off) 15 25 35 45 55 65 75 i s (off) 02373-009 temperature (c) current (na) 0.1 1 10 100 figure 10. leakage current as a function of temperature, v dd = 5 v 0.05 ?0.05 58 5 02373-012 0 ?15 0.01 1000 frequency (mhz) on response (db) 0.04 0.03 0.02 0.01 0 ?0.01 ?0.02 ?0.03 ?0.04 15 25 35 45 55 65 75 i s , i d (on) i d (off) i s (off) v dd = 3.0v v ss = 0v temp = 25c v d = 2v/1v v s = 1v/2v 02373-010 figure 11. leakage current as a function of temperature, v dd = 3 v 0 ?100 0.01 1000 frequency (mhz) attenuation (db) 0.1 1 10 100 ?20 ?40 ?60 ?80 02373-011 figure 12. off isolation vs. frequency figure 13. crosstalk vs. frequency 0.1 1 10 100 ?5 ?10 02373-013 . 5 figure 14. bandwidth 0 ?7 02 voltage (v) q inj (pc) ?1 ?2 ?3 ?4 ?5 ?6 0.5 1.0 1.5 2.0 v dd = 3v v dd = 5v 02373-014 figure 15. charge injection vs. source voltage
adg774a rev. b | page 9 of 16 test circuits i ds v1 sd v s r on = v1/i ds 02373-019 figure 16. on resistance sd v s a a v d i s (off) i d (off) 02373-020 figure 17. off leakage sd a v d i d (on) nc nc = no connect 02373-021 figure 18. on leakage 0.1f v dd gnd en 50? v out v s in d1 v in s1a adg774a 50 ? network analyzer 0 2373-024 figure 19. bandwidth 0.1f v dd gnd en 50? v out v s in d1 v in s1a adg774a 50? network analyzer 50 ? 02373-025 figure 20. off isolation 0.1f v dd gnd en in v in r l 50? v s d2 s1a adg774a d1 50? network analyzer v out s2a 50? 02373-026 figure 21. channel-to-channel crosstalk
adg774a rev. b | page 10 of 16 0.1f 5 v v s in sd v dd gnd r l 100 ? c l 35pf v out en 3v 50% 50% 90% 90% v in v out t on t off 02373-022 figure 22. switching times 0.1f 5 v v s en s1a d1 v dd gnd r l 100 ? c l 35pf v out s1b decoder v s 80% 80% v in v out t d t d 50% 50% 3v 0v v s 0 2373-023 figure 23. break-before-make time delay 5 v en s1a v dd c l 1nf s1b v in v out 3v q inj = c l v out v out c l 1nf c l 1nf c l 1nf d1 v out d2 v out d3 v out d4 v out adg774a 1 of 2 decoder in s2a s2b s3a s3b s4a s4b v s r s 02373-027 figure 24. charge injection
adg774a rev. b | page 11 of 16 terminology v dd most positive power supply potential. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. in logic control input. en logic control input. r on ohmic resistance between d and s. ? r on on resistance match between any two channels, that is, r on max ? r on min. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on the d and s terminals. c s (off) off switch source capacitance. c d (off) off switch drain capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. see figure 22 . t off delay between applying the digital control input and the output switching off. t d off time or on time measured between the 80% points of both switches when switching from one address state to another. see figure 23 . crosstalk a measure of unwanted signal that is coupled through from one channel to another because of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off switch. bandwidth frequency response of the switch in the on state measured at 3 db down. distortion r flat(on) /r l
adg774a rev. b | page 12 of 16 application circuits adg774a transformer tx1 tx2 rx1 rx2 10 base tx+ 10 base tx? 100 base tx+ 100 base tx? 10 base tx+ 10 base tx? 100 base tx+ 100 base tx? 10 base tx 100 base tx rj45 02373-015 figure 25. full duplex transceiver tx1 rx1 02373-016 120 ? 100 ? 02373-017 02373-018 figure 26. loop back figure 27. line termination figure 28. line clamp
adg774a rev. b | page 13 of 16 outline dimensions compliant to jedec standards mo-137-ab 16 9 8 1 pin 1 seating plane 0.010 0.004 0.012 0.008 0.025 bsc 0.010 0.006 0.050 0.016 8 0 coplanarity 0.004 0.065 0.049 0.069 0.053 0.197 0.193 0.189 0.158 0.154 0.150 0.244 0.236 0.228 figure 29. 16-lead shrink small outline package [qsop] (rq-16) dimensions shown in inches 1 0.50 bsc 0.60 max p i n 1 i n d i c a t o r 1.50 ref 0.50 0.40 0.30 0.25 min 0.45 2.75 bsc sq top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicato r 0.90 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 3.00 bsc sq * 1.65 1.50 sq 1.35 16 5 13 8 9 12 4 exposed pad (bottom view) * compliant to jedec standards mo-220-veed-2 except for exposed pad dimension. figure 30. 16-lead lead frame chip scale package [lfcsp_vq] (cp-16-3) dimensions shown in millimeters ordering guide model temperature range package description package option adg774abrq ? 40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg774abrq-reel ? 40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg774abrq-reel7 ? 40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg774abrqz 1 ? 40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg774abrqz-reel 1 ? 40c to +85c 16-lead shrink small outline package [qsop] rq-16 adg774abrqz-reel7 1 ? 40c to +85c 16-lead shrink small outline package [qsop] rq-16 ADG774ABCPZ-REEL ? 40c to +85c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-3 1 z = pb-free part.
adg774a rev. b | page 14 of 16 notes
adg774a rev. b | page 15 of 16 notes
adg774a rev. b | page 16 of 16 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c02373-0-8/06(b)

▲Up To Search▲

Price & Availability of ADG774ABCPZ-REEL

	To Download ADG774ABCPZ-REEL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .